Traditionally, memory controllers have relied on external clocks to be able to write data to or read data from a synchronous memory subsystem (e.g. memory storage devices). Providing these clocks between the memory controller and the memory subsystem typically involves the use of multiple pins on memory controller modules and memory subsystems. These pins and clock traces on controller modules and memory subsystems often consume much needed space on the memory subsystem's board, module, or interface.
FIG. 1 illustrates a conventional prior art memory controller 102 and memory subsystem 104 configuration. In computer implementations, the memory controller 102 is typically a component on the motherboard which manages communications to and from the memory subsystem 104. A memory subsystem 104 is typically a separate module (such as a dual in-line memory module (DIMM) or single in-line memory module (SIMM)) which stores and provides data as directed by the memory controller.
A typical memory controller-to-memory subsystem interface includes a bus with multiple command/address lines, data lines, write clock lines, and/or read clock lines. The command/address lines allow the memory controller 102 to indicate to the memory subsystem 104 to store data or retrieve data. The data lines (either bi-directional or uni-directional) serve to transmit data between the memory controller 102 and the memory subsystem 104.
When the memory controller 102 stores or writes data to the memory subsystem 104, it provides the memory subsystem 104 a clock (write clock) from which to synchronize and sample the data sent. That is, the memory subsystem 104 needs a clock from which to synchronize the data received over the data lines so that it may be correctly detected. Where multiple data lines are used, the memory controller typically provides one clock per one or more data lines.
Similarly, the memory controller 102 needs to synchronize and sample data retrieved from the memory subsystem 104. Conventionally, the memory subsystem provides read clocks to the memory controller for this purpose. Typically, the memory controller 102 provides one clock per one or more data lines. Thus, when the number of data lines increase so do the number of corresponding clock lines, inputs, pins, and/or traces.
Dynamic random access memory (DRAM) is a common type of memory storage device used in computers and other electronic devices. As described above, traditional synchronous DRAM (SDRAM) memory subsystems employ externally generated clocks to synchronize writing data to and reading to from a DRAM module. In the case of double data rate (DDR) DRAMs, additional strobe lines are employed to enable the rate doubling. For example, in DDR SDRAM systems, a system clock plus one strobe per four to eight data bus lines is typically employed to read data. On a sixty-four bit/line wide memory data bus this equates to eight to sixteen read clock signal pins on the controller, motherboard, and/or memory module connector.
As the speed of memory subsystems and data transmission increase, the number of clocks and strobes needed to achieve reliable data transmission increases, adding to the cost and detracting from the feasibility of designing and implementing such subsystems.